Microsoft Word - Digital Logic Design v_4_6a

declarations.

Once a library is included using the library statement, use statement shown below is used to include
the desired library package in the design.

use package_name

When using VHDL functions, the description of function includes guidance on which library packages
are required for the function.

Example – The following two statements brings in all the definitions from the IEEE standard 1164
package:

library IEEE;

use IEEE.Std_Logic_1164.all;

Std_Logic_1164.all contains the following:

• type std_ulogic: unresolved logic type of 9 values;


• type std_ulogic_vector: vector of std_ulogic;


• function resolved resolving a std_ulogic_vector into std_ulogic;


• subtype std_logic as a resolved version of std_ulogic;


• type std_logic_vector: vector of std_logic;


• subtypes X01, X01Z, UX01, UX01Z: subtypes of resolved std_ulogic containing the
  values listed in the names of subtypes (i.e. UX01 contains values 'U', 'X', '0', and '1', etc.);


• logical functions for std_logic, std_ulogic, std_logic_vector and std_ulogic_vector;


• conversion functions between std_ulogic and bit, std_ulogic and bit_vector,
  std_logic_vector and bit_vector and vice-versa;


• functions rising_edge and falling_edge for edge detection of signals.


• x-value detection functions, is_x, which detect values 'U', 'X', 'Z', 'W', '-' in the actual
  parameter.

IEE 1164 Standard Logic Package (released in the 1980s) defines many functions that operate

on the standard types of std_logic and std_logic_vector. IEEE 1164 replaces these proprietary

data types (which include systems having four, seven, or even thirteen unique values) with a

standard data type having nine values, as shown below:

Value Description

'U' Uninitialized

'X' Unknown

'0' Logic 0 (driven)

'1' Logic 1 (driven)

'Z' High impedance

'W' Weak 1

'L' Logic 0 (read)

'H' Logic 1 (read)

'-' Don't-care

These nine values make it possible to accurately model the behavior of a digital circuit during

simulation.

 The std_ulogic data type is an unresolved type, meaning that it is illegal for two values (such

as '0' and '1', or '1' and 'Z') to be simultaneously driven onto a signal of type std_ulogic.

 If you are describing a circuit that involves multiple values being driven onto a wire, then you

will need to use the type std_logic. Std_logic is a resolved type based on std_ulogic.