Microsoft Word - Digital Logic Design v_4_6a

(lily) #1
Resolved types are declared with resolution functions.

 Example: NAND gate coupled to an output enable
Note: Even though it is not necessary we will use the resolved type “std_logic”


library ieee;
use ieee.std_logic_1164.all;

entity nandgate is
port (A, B, OE: in std_logic; Y: out std_logic);
end nandgate;

architecture arch1 of nandgate is
signal n: std_logic;
begin
n <= not (A and B);
Y <= n when OE = '0' else 'Z';
end arch1;
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