8.7. Behavioral Design
VHDL design may be conducted using structural or behavioral approach. In structural design, the basic
building blocks are defined using components and the rest of design defines the interconnection between
these components. Structural design is the closest approximation to using the physical component with
wiring diagram. In other words, it is the simply a textual description of a schematic.
The strength of VHDL is based on its ability to compile description of circuit behavior to a fully defined and
implementable design. This is referred to as behavioral design which is much simpler than the structural
design and is commonly used for design.
Behavioral design relies of data flow elements to define functionality which is described in the next
section. Another useful VHDL statement is process:
Characteristics
A process is a list of sequential statements that executes in parallel with other concurrent
statements and processes in the architecture..
Using process, a designer can specify a complex interaction of signals and events in a way that
executes in essentially zero simulated time during the simulation. This characteristic is useful in
synthesizing and modeling combinational or sequential circuits.
A process statement can be used anywhere a concurrent statement can be used.
A process statement has visibility within the scope of an enclosing architecture. This means that
the types, signals, constants, functions and procedures defined in architecture are visible to the
process. But the variable, type, constant, function and procedure defined in the process are not
visible to the architecture.
A process can not declare signals therefore only variable declarations are available in Process.
Syntax of a VHDL process statement
process (signal_name, signal_name, ... , signal_name)
type declarations
variable declarations
constant declarations
function declarations
procedure declarations
begin
sequential_statement...
sequential_statement
end process;
As a quick reminder, process executes statements sequentially and does not allow signal declaration
within its scope. As discussed earlier, variable assignment operation is “:= ” which is different from
signal assignment “<=”. But the declaration is similar to signal declaration as shown below:variable variable_names : variable_type; Process operations
A process is always either running or suspended. The list of signals passed is called the “sensitivity
list” which determines when the process runs. Below is an overview of process life cycle:
Process is initially suspended.
When any of the signals in the sensitivity list changes value, the process starts execution with
the first sequential-statement in the process.