Microsoft Word - Digital Logic Design v_4_6a

(lily) #1

 Carry-Anticipation or Carry Look-Ahead Adder
This solution reduces the settling time of adders.
 Ripple-Carry for an n-bit adder will have settling time of 3tp + 2(n-1)to since each stage will
generate an output based on the last stage and would require 2tp (Gate propagation) to
complete the result.
 Carry-Look-Ahead basically adds the circuitry to calculate the carry without having to wait for
the propagation from each stage, effectively cutting the settling time to 6tp for an n-bit adder
when n>2. For a 1-bit adder, the setting time is 3tp, and for a two-bit adder, the settling time is
4tp.


 Carry-Save Adders
Carry-Save Adders (CSAs) are designed to add more than two operands.
 CSA’s are designed using Full Adders (FA)



  • The carry from one level is fed into the next significant bit of the next stage.

  • The last stage shifted by one to the left but no new output is generated.

  • The number of rows of Adders = (The number of operands to be added) - 1
     Example (five operands):


A0 Operand 1
B0 Operand 2
+ C0 Operand 3
-----------.
S10 Sum, Row 1
CO11 Carry Row 2 (carry Save)
+ D0 Operand 4
---------------.
S21 S20 Sum, Row 2
CO21 Carry Row 3 (carry Save)
+ E0 Operand 5
---------------.
S31 S30 Sum, Row 1
CO32 CO31 Carry Row 4 (carry Save)
+ CO43 CO42 CO41 Carry Row 4 (no carry Save)
-----------------------------------.
S43 S42 S41 S40 Sum, Row 4 (Last Row)

A B CI


S 0


FA0


CO S


A0 B0 SUB


A B CI


S 1


FA1


CO S


A1 B1


A B CI


S 2


FA2


CO S


A2 B2


A B CI


S 3


FA3


CO S


A3 B3


CO


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