Microsoft Word - Digital Logic Design v_4_6a

 Dynamic Hazards

A dynamic hazard occurs when an output changes from 0 to 1 or from 1 to 0.

(in static hazard case: output before and after the glitch was the same)

• Typically dynamic hazards are produced by multi-level or cascading logic circuits


• Example F= A⊕B⊕C which means F=1 when odd number of inputs are 1. Identify
  dynamic hazards in this circuit.

Step 1. Do the K-map

Depending on the amount delay through each gate, you may or may not have a dynamic

hazard. Typically, simulation software such as B2 Logic , PSpice, and Electronic Work

Bench is used to compare maximum and minimum propagation delay for each component to

find any dynamic hazards.

If we assume the right amount of delay through the gate, it can be shown that we can cause

dynamic hazards in the following paths:

Dynamic hazards are by far the hardest problem to identify. Once the hazards are identified, strategic
delays can be implemented to correct the problems.

Logic 1 glitch

Cell 5 to 2 or Cell 6 to 1

causes Dynamic 1 to 0 hazard

F2 (1 0)

t

Logic 0 glitch

Cell 2 to 5 or Cell 1 to 6

causes Dynamic 0 to 1 hazard

t

F2 (01)

00 11

12 03

06 17

14 05

00

01

11

10

AB C 0 1

Logic 1 glitch

Dynamic 1 to 0 hazard

F2

t

Logic 0 glitch

Dynamic 0 to 1 hazard

t