4.3. Asynchronous Sequential Logic Issues
A circuit that uses latches (flip-flops) but does not use a clock to synchronize all signals is called
Asynchronous Sequential Logic. Here we will explore the issues that may be present in asynchronous
design.
Race Condition
For example (SR flip-flop)
S R Q = 000
S changes to 1 S R Q = 100 (unstable or transitory state) Q+ = 1 (refer to table)
S R Q = 101 (after delay) A stable state. This state will be maintained until the External input
changes.If the S and R inputs change quickly (one after another) before the output settles into a new
stable state, the input provides a race condition (each trying to change the output first). If the
output becomes a predictable stable state, then the race is non-critical.A critical race occurs if the circuit output ends in an unpredictable stable state. Example of a Critical Race
S R Q = 110
SR are changed simultaneously to 00- S may change first S R Q = 010 Q+ = 0 Stable state
next R changes, SRQ = 0 0 0 Q+ = 0 Stable state - R may change first S R Q = 100 Q+ = 1 Unstable state
next S changes, SRQ = 0 0 1 Q+ = 1 Stable state