Reversing : The Hacker's Guide to Reverse Engineering

In terms of the actual execution of operations, the architecture provides four

execution ports (each with its own pipeline) that are responsible for the actual

execution of instructions. Each unit has different capabilities, as shown in

Figure 2.4.

Figure 2.4 Issue ports and individual execution units in Intel NetBurst processors.

Po rt 0

Double Speed ALU

ADD/SUB

Logic Operations

Branches

Store Data Operations

Floating Point Move

Floating Point Moves

Floating Point Stores

Floating Point Exchange (FXCH)

Po rt 1

Double Speed ALU

ADD/SUB

Floating Point Execute

Floating Point Addition

Floating Point Multiplication

Floating Point Division

Other Floating Point

Operations

MMX Operations

Integer Unit

Shift and Rotate

Operations

Po rt 2

Memory Loads

All Memory Reads

Po rt 3

Memory Writes

Address Store Operations

(this component writes the

address to be written into

the bus, and does not send

the actual data).

66 Chapter 2