Hardware Manual PCD 1 / PCD 2 Series│Document 26 / 737│Edition EN 15│2008-07-22

Saia-Burgess Controls AG

PCD2.H150

Input/output (I/O) modules

5

Block diagram

CLK

/CLK

D

/D

A 12

A 13

User PROM

FPGA

(Field Programmable

Gate Array)

PCD Bus

Input filter and adaptation 24V to 5V

Output amplifier 5 .to. 32 VDC (Uext)

Clock

/Clock

Data

/Data

Output 12

A 14

A 15

Output 13

Output 14

Output 15

For further details, please refer to manual 26/761 “PCD2.H150 - SSI interface for

absolute encoder”.

Watchdog: This module cannot be used on the base address 240 (or 496 for the

PCD2.M17x), because it would interact with the watchdog, and would cause a

malfunction.

For details, please refer to the “Watchdog” section, which describes the correct use of

the watchdog in conjunction with PCD2 components.

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