To a large extent, the minimum size of the features being etched,
and therefore the number of transistors that can be crammed into
a given area of the wafer, are dictated by the wavelength of the
light. The shorter the wavelength used, the smaller the features.
In simple terms, the smallest current production processes
demand EUV technology and TSMC absolutely dominates in its
use of EUV. Last year, TSMC shipped nearly three-quarters of all
semiconductors produced via EUV lithography, Samsung a little
under a quarter, while Intel barely factored.
As for overall advanced node capacity, in 2021 TSMC was
tooled up for nearly 150,000 7nm-class wafers per month and
over 100,000 5nm class wafers. Intel’s 10nm node or Intel 7
capacity was around 50,000 wafers.What’s more, late last year TSMC reportedly began trial
production of its next major advance, 3nm, with full-scale
production slated for the second half of this year. Next year,
TSMC is expected to have a staggering 120,000 wafer-per-month
3nm capacity. That 3nm node, incidentally, is expected to offer a
transistor density of 300 million per square millimeter.
Meanwhile, Intel’s 7nm capacity (the node now branded Intel
4) is expected to be just 20,000 wafers per month. No wonder
Intel has decided to outsource some of its cutting-edge chips to
TSMC for manufacture over the next few years while it gets its
own foundries in order.
If that’s the good news, the bad is that the eventual physical
limitation to the existing basis of Moore’s Law remains. There’s
only so far you can go shrinking transistors and other features
using conventional semiconductor tech. TSMC’s Wong has
pointed out that its current FinFET transistor technology is
already approaching the atom scale.
“The fin is about 10nm, or rather slightly less than 10nm,” Wong
says, “and, if you use an extremely high-resolution transmission
electron microscope, you can actually see the individual atoms.
You can count them. You still need both hands and maybe toes to
count the number of atoms in a fin, but not much more than that.
“So, if you go by two-dimensional device scaling by itself—
which is a really powerful knob that we have in making new
transistors, in providing you density—you quickly see that we’re
down to very few atoms, and very soon you’ll run out of atoms.Above: TSMC has been making 5nm chips for over 18 months.
Left: TSMC beat Intel to EUV lithography, which is part of the
reason why it has a clear node advantage.MAR 2022 MAXIMU MPC 33
© TSMC, ASML