0195136047.pdf

132 TIME-DEPENDENT CIRCUIT ANALYSIS

S t = 0

(a)

iC(t)

vC(t)

1 Ω

5 Ω vx(t)

10 V 4 Ω

5 F

b

+ − a

+

−

+

−

Figure E3.2.4

(b)

Short 1 Ω

5 Ω

4 Ω

S RTh = 5 + 1 = 6 Ω

b

a

S

+10 V− +

−

(c)

vC, ss(t) = −10 V

1 Ω

5 Ω

4 Ω

Open

b

a

S

+10 V− +

−

+

−

vx(o−) vC(o−) = −40/9 V

t = o−

1 Ω

5 Ω

4 Ω

Open

b

a

(d)

Solution

(Note that the procedure is similar to that of Example 3.2.3.) The Thévenin resistance seen by the

capacitor fort>0 is found by considering the circuit fort>0 while setting all ideal sources to

zero, as shown in Figure E3.2.4(b).

The time constant of the capacitor voltage isτ=RThC= 6 × 5 =30 s. The steady-state

value of the capacitor voltage fort>0,vC,ss(t), is found by replacing the capacitor by an open

circuit (since the source is dc in the circuit fort>0), as shown in Figure E3.2.4(c).

The initial capacitor voltage att= 0 −,vC(0−), is found from the circuit fort<0 as the

steady-state value of the capacitor voltage fort<0. Figure E3.2.4(d) is drawn fort<0by

replacing the capacitor with an open circuit (since the source is dc).

One can solve forvC( 0 −)to yieldvC

(

0 −

)

=− 40 /9V=vC

(

0 +

)

, by the continuity of the

capacitor voltage. Then the solution for the capacitor voltage fort>0 can be written as

vC(t)=

[

vC

(

0 +

)

−vC,ss

(

0 +

)]

e−t/(RThC)+vC,ss(t), fort> 0