0195136047.pdf

282 DIGITAL BUILDING BLOCKS AND COMPUTER SYSTEMS

BD A

+ B

A CD

Half-adder

C

X C Z

W

Full adder

Y

BD

A

Half-

adder

C

C B

W

X

D

A

Half-

adder

“Carry” from

previous digit

“Carry” to

next digit

C

Y

Z

AB

00

01

10

11

CD

00

01

01

10

(a)

(b)

Inputs Outputs

WX

00

00

01

01

YZ

00

01

01

10

10

10

11

11

C 0 1 0 1 0 1 0 1

01

10

10

11

Inputs Outputs

WA

XB

YDZ

+

Figure 6.1.10(a)Half-adder and its truth table.(b)Full adder and its truth table.

WX

Y

FA C

Z

A 3 B 3

S 4 S 3

WX

Y

FA C

Z

A 2 B 2

S 2

WX

Y

FA C 0 +

Z

A 1

A 3

B 1

S 1

WX

Y

FA C

Z

A 0 B 0

S 0

S 4

A 2

S 3

A 1

S 2

A 0

B 3 B 2 B 1 B 0

S 1 S 0

Figure 6.1.11Addition of 4-digit binary numbers.

EXAMPLE 6.1.7

Refer to Figure 6.1.10(a) of the half-adder and its truth table for adding two single-digit binary

numbers,AandB, to yield a two-digit numberCD. Using the SOP method, develop a circuit to

generateCandD.

Solution

In terms of the four possible gates (with an output of 1 only) shown in Figure 6.1.8, the circuit in

Figure E6.1.7(a) can be drawn. Note that the resulting circuit will not be minimal, as is usually

the case with the SOP method. The truth table can be realized with only three gates, using the

circuit shown in Figure E6.1.7(b). The student is encouraged to verify by constructing its truth

table.