0195136047.pdf

6.1 DIGITAL BUILDING BLOCKS 293

EXAMPLE 6.1.14

The positive-edge triggered D flip-flop is given the inputs shown in Figure E6.1.14(a), with a zero
initial value ofQ. Draw the timing diagram.

D

Ck

0

1

1

0

Q

1

0

D

Ck

0

(a)

(b)

1

1

0

Figure E6.1.14

Solution

Qis illustrated in Figure E6.1.14(b) as a function of time.

In order to avoid the input conditionSR=11, an inverter is included, as shown in Figure
6.1.21.SRcan be either 01 or 10. ForSR=10, the flip-flopsets(i.e.,QQ ̄ =10) whereas for
SR=01 itresets(i.e.,QQ ̄=01). Thus, the output replicates the input state, but with a delay
equal to the time for information to propagate through the flip-flop.
Most commercially available flip-flops also include two extra control input signals known as
presetandclear. When activated, these input signals will set (Q=1) or clear (Q=0) the flip-
flop, regardless of other input signals. Figure 6.1.22(a) shows the block diagram of a positive-edge
triggered D flip-flop with preset and clear control signals; Figure 6.1.22(b) gives the functional
truth table for this device. Note that the clock is the synchronizing element in a digital system. The
particular device described here is said to be positive-edge triggered, or leading-edge triggered,
since the final output of the flip-flop is set on a positive-going clock transition.
Figure 6.1.23 shows a realization of the D flip-flop using six NAND gates, in which the output
part is very similar to the SRFF of Figure 6.1.18 and the other four gates are used to translate the
D-type control instructions into a form that the SRFF can use.

SQ

R

Data

Q

Figure 6.1.21Flip-flop with inverter.