0195136047.pdf

294 DIGITAL BUILDING BLOCKS AND COMPUTER SYSTEMS

Preset Clear Ck D QQ

01

01

10

10

Not allowed

(b)

Inputs Outputs

01

00

00

11

10

dd

0

1

dd

D dd

Ck

Clear

Preset

Q

Q

(a)

Figure 6.1.22Positive-edge triggered

D flip-flop with preset and clear.(a)

Block diagram.(b)Truth table. NOTE:

dstands for don’t-care condition. The

symbol indicates the occurance of a

positive transition in the clock timing.

The symbol>(knife edge) drawn next

to the clock input in the block diagram

indicates edge-triggered feature.

Q

Preset

Clear

Clock

D

Q

Figure 6.1.23Realization of D flip-flop with six NAND gates.

JK FLIP-FLOP(JKFF)

The block diagram, truth table, and a practical realization of the JKFF are shown in Figure

6.1.24. The JKFF differs from an SRFF in that outputQis fed back to theK-gate input

andQ ̄ to theJ-gate input. AssumingQQ ̄ =01, gateBis disabled byQ =0 (i.e.,F =

1). The only way to make the circuit change over is for gateAto be enabled by making

J = 1 andQ ̄ = 1 (which it is already). Then when Ck=1, all inputs to gateAare 1

andEgoes to zero, which makesQ=1. WithQandFboth equal to 1,Q ̄ = 0, so the

flip-flop has changed state. Note that the input conditionJK= 11 is allowed, and in this

condition, when the flip-flop is clocked, the output always changes state; thus it is said to

toggle.

If the clock pulse is short enough to permit the flip-flop to change only once, the JKFF

operates well. However, with modern high-speed ICs araceis more likely to occur, which is a

condition in which two pulses are intended to arrive at a destination gate in some specific order,

but due to each one racing through different paths in the logic with a different number of gates,

the propagation delays stack up differently and the timing order is lost. This can be eliminated

by introducing delays in the feedback paths between outputs (QandQ ̄) and inputs (JandK). A

better solution to the problem is the master–slave JKFF.