6.2 DIGITAL SYSTEM COMPONENTS 295
D
C
A
E
F
J
Ck
K B
Q
J Q
Ck
Q
KQ
(a) (c)
JK
00
01
10
11
Qn+ 1 Qn+ 1
Qn Qn
01
10
(b)
Inputs Outputs
Qn Qn
Figure 6.1.24JK flip-flop.(a)Block diagram.(b)Truth table.(c)A realization.
MASTER–SLAVEJKFF
Figure 6.1.25 illustrates a master–slave JKFF, in which gatesA, B, C,andDform themaster
flip-flop andT, U, V,andWform theslave. The output of the master–slave JKFF can be predicted
for all combinations ofJandKand for any duration of clock pulse. Thus it is the most versatile
and universal type of flip-flop. SRFFs are also available in master–slave configuration.
Ck=1 enables the master;Ck ̄ =0 disables the slave. LetQQ ̄=10 andJK=11 before
the occurrence of a clock pulse.Bis enabled byQ=1 so that when the clock pulse arrives
(i.e., Ck=1),Fgoes to zero andQ ̄Mto 1. Now withE=1 andQ ̄M=1,QMgoes to zero so
that the master has been reset. However, the slave remains disabled until Ck goes to zero. Note
that the slave, at this stage, is essentially an SRFF with inputsSandRequal toQMandQ ̄M,
respectively. Thus, when Ck goes to zero,Ck ̄ goes to 1 and the slave is now reset by its inputs
QMQ ̄M=01. But the feedback toJand K cannot cause a race because, with Ck=0, the master
is disabled.
W
V
U
T
B
J A
K D
E C
F
Master Slave
Q
Q
Ck
Ck
QM
QM
Figure 6.1.25Master–slave JK flip-flop.
6.2 Digital System Components
The basic combinational and sequential building blocks were introduced in Section 6.1. The
reason that digital systems are so inexpensive and yet so powerful is that they consist of very
