0195136047.pdf

6.2 DIGITAL SYSTEM COMPONENTS 303

EXAMPLE 6.2.2

Show the logic diagram of an 8-to-1 multiplexer.

Solution

The logic diagram is depicted in Figure E6.2.2.

A 2 A 1 A 0

Q

I 0

I 1

I 2

I 3

I 4

I 5

I 6

I 7

Figure E6.2.2

EXAMPLE 6.2.3

Given the block diagram for a 4-bit shift-left register shown in Figure E6.2.3(a), draw the output
(Q 0 ,Q 1 ,Q 2 ,Q 3 , and data out) as a function of time for the clock, clear, and data-in signals given
in Figure E6.2.3(b).

Clr Clr Clr Clr

Clear

Q 3

Clock

Data in

(a)

Ck 3

D 3

Q 3

Data out Q^2

Ck 2

D 2

Q 2

Q 1

Ck 1

D 1

Q 1

Q 0

Ck 0

D 0

Q 0

Figure E6.2.3