0195136047.pdf

306 DIGITAL BUILDING BLOCKS AND COMPUTER SYSTEMS

does not receive the first change instruction, but it does receive the second one. At the time of the

second change instruction,Q 1 is still 1; it changes to 0 shortly afterward, but by that time FF2

has already been triggered. Similarly, FF3 is triggered only whenQ 1 andQ 2 are both equal to 1.

Thus, from the timing diagram, the successive states ofQ 3 Q 2 Q 1 can be seen as 000, 001, 010,

011, 100, 101, 110, 111, 000, 001,... , as required for a counter.

Note that in a synchronous counter, all the flip-flops change at the same time (unlike in a

ripple counter). The total delay is then the same as the propagation delay of a single flip-flop.

D

Ck

FF2 FF3

FF1

Q 3

Q 3

D

(a)

(b)

Ck

Q 2

Q 1

Q 2

Q 3

Q 2

D

Ck

Input

Input

Q 1

Q 1

Figure E6.2.5(a)Block diagram.(b)Timing diagram.

Digital-to-Analog (D/A) Converters

For the results of digital computations to be used in the analog world, it becomes necessary to

convert the digital values to proportional analog values. Figure 6.2.8 shows the block diagram of

a typical digital-to-analog (D/A) converter, which accepts ann-bit parallel digital code as input

and provides an analog current or voltage as output. For an ideal D/A converter, the analog output

for ann-bit binary code is given by

Vo=−Vref(b 0 +b 1 × 2 −^1 +b 2 × 2 −^2 +···+bn− 1 × 2 −n+^1 ) (6.2.1)

where

Resistor and

switching

network

Reference voltage

Digital input

Analog output

I

R

b 0

b 1

Vo

bn-1 +

−

Figure 6.2.8Block diagram of

typical D/A converter.