0195136047.pdf

310 DIGITAL BUILDING BLOCKS AND COMPUTER SYSTEMS

+

−

V 1

V 2

D/A converter

Reset

Digital output

Analog input

Binary counter

Figure 6.2.13Block diagram of counter-

controlled A/D converter.

to be converted, then the MSB is reset to 0 and the next bit is tried as the MSB. On the other

hand, if the signal to be converted is larger than the D/A computer output, then the MSB remains

1. This procedure is repeated for each bit until the binary equivalent of the input analog signal
   is obtained at the end. This method requires onlynclock periods, compared to the 2nclock
   periods needed by the counter-controlled A/D converter, wherenis the number of bits required
   to encode the analog signal. The National ADC 0844 is a popular 8-bit A/D converter based on
   the SAR.

DUAL-RAMP(DUAL-SLOPE) A/D CONVERTER

Figure 6.2.15(a) shows the block diagram of a dual-ramp (dual-slope) A/D converter. After a

start-of-conversion pulse, the counter is cleared and the analog inputVinbecomes the input of the

ramp generator (integrator). When the output of the ramp generatorVoreaches zero, the counter

starts to count. After a fixed amount of timeT, as shown in Figure 6.2.15(b), the output of the

ramp generator is proportional to the analog input signal. At the end ofT, the reference voltage

Vrefis selected, when the integrator gives out a ramp with a positive slope. AsVoincreases, the

counter is incremented untilVoreaches the comparator threshold voltage of 0 V, when the counter

+

−

V 1

V 2

N-bit D/A

Start conversion

N-bit digital output

Analog input

N-bit successive-

approximation

register (SAR)

MSB LSB

Clock

Figure 6.2.14Block diagram of suc-

cessive-approximation A/D converter.