0195136047.pdf

398 TRANSISTOR AMPLIFIERS

+

−

VG VDD

R 1

R 2

G

S

D

RS

RD

Figure 8.2.2Biasing ann-channel enhancement

MOSFET.

iD=K(vGS−VT)^2 (8.2.14)

in whichVTandKare specified based on the transfer characteristic [Figure 7.4.8(a)] in the

manufacturer’s data sheets.

The load-line equation is

iD=

VG−vGS

RS

(8.2.15)

The required gate–source voltageVGSQat the operating point is then

VGSQ=VT+

√

IDQ

K

(8.2.16)

VDSQcan then be selected to yield a desired operating point on theID–VDSstatic characteristics of

the device. It follows then

RS+RD=

VDD−VDSQ

IDQ

(8.2.17)

By trading off ac gain (largerRD) versus dc stability (largerRS),RDandRSneed to be chosen.

OnceRSis chosen, thenVGis set by

VG=VGSQ+IDQRS (8.2.18)

Finally,R 1 andR 2 can be selected arbitrarily to yieldVGwhile keeping both large enough to

maintain a large gate impedance. The outlined approach is best illustrated by an example.

EXAMPLE 8.2.2

Given ann-channel enhancement MOSFET havingVT=4V,K= 0 .15 A/V^2 ,IDQ= 0 .5A,

VDSQ=10 V, andVDD=20 V. Using the dc design approach outlined in this section, determine

VGSQ,VG,RD,RS,R 1 , andR 2.

Solution

Applying Equation (8.2.16),

VGSQ=VT+

√

IDQ

K

= 4 +

√

0. 5

0. 15

= 5 .826 V