0195136047.pdf

428 DIGITAL CIRCUITS

Using the transistor switch, logic gates can be constructed to perform the basic logic functions

such as AND, OR, NAND, NOR, and NOT. Since the individual gates are available in the form of

small packages (such as the dual-in-line package, or DIP), it is generally not necessary to design

individual gates in order to design an overall digital system. However, the designer needs to

observe fan-out restrictions (i.e., the maximum number of gates that may be driven by the device),

fan-in restrictions (i.e., the maximum number of gates that may drive the device), propagation

delays, proper supply voltage to the unit, and proper connections to perform the intended logic

function. Gates of the same logic family can be interconnected since they have the same logic

voltage levels, impedance characteristics, and switching times. Some of the logic families are

discussed in this section.

DTL (Diode Transistor Logic) Gate

A circuit realization of a NAND gate will now be developed. By connecting NAND gates together

in various ways, one can synthesize other gates and flip-flops. Thus in principle, a single NAND

gate circuit, repeated many times, would be sufficient to build up digital systems.

One possible NAND gate circuit is shown in Figure 9.2.1, in which it can have as many inputs

as desired (indicated by the dashed-line inputC), and typical values ofVCC=5V,RA=2k,

RC=5k, andβ=50. We shall now consider the two inputsAandBthat are quite adequate for

our discussion, with the high range defined to be 4 to 5 V and the low range defined to be 0 to 0.5 V.

While the input voltagesvAandvBare constrained to lie inside the high or low range of

the allowed voltage ranges, the resulting output voltagevFis supposed to be inside the high or

low range as well. For different combinations ofvAandvB, we need to findvF. Since the circuit

consists of no less than five nonlinear circuit elements (DA,DB,D 1 ,D 2 , andT 1 ), an approximation

technique is used for analysis, while taking the voltage across a current-carrying forward-biased

pnjunction to be 0.7 V. The reader may have realized that it is not obvious at the start which

diodes are forward-biased and which are reverse-biased. Hence a guessing procedure is used in

which a guess is made and checked for self-consistency.

Let us start by lettingvA=vB=0, in which case a probable current path is fromVCCdown

throughRAand through inputsAandB. Since this guess implies current flow throughDAandDBin

the forward direction, we may guess that the voltage atXis 0.7 V. There is also a current path from

Xdown to ground throughD 1 andD 2 and the base–emitter junction of the transistor. Even though

the sign of the guessed voltage is correct to forward-bias these three junctions, its magnitude of

0.7 V is insufficient since 2.1 V (or 3× 0 .7) is needed to make current flow through this path.

TheniB=0; the transistor is cut off; and the output voltagevF =VCC=5 V, assuming that

RA

DA

DC

A

C

X

VCC

RC iL

iB

T 1

D 1 D 2

FOutput

Inputs

VCC

DB

B

Figure 9.2.1DTL NAND gate.