0195136047.pdf

444 DIGITAL CIRCUITS

Figure 9.3.1Continued

12 4

(a)

t, ms

Vi, V

− 5

3

Figure P9.3.2(a)Input.(b)JFET characteris-

tics.

iD, mA

vDS, V

vGS = 0 V

−1 V

−2 V

−3 V

−4 V

−5 V

10

9 8 7 6 5 4

024681012141618

(b)

20 22 24

3

2

1

S

iG = 0

vDS

vGS

iD

D

+

+

−−

G

9.3.6Explain the principle of operation of the CMOS

transmission gate shown in Figure 9.3.6.

9.3.7Consider the CMOS NAND gate shown in Figure

P9.3.7. Explain its operation and the approximate

behavior of transistors in CMOS logic.