1.15. SWITCH()/CASE/DEFAULT
lui $a0, ($LC0 >> 16) # "zero"
lw $t9, (puts & 0xFFFF)($gp)
or $at, $zero ; load delay slot, NOP
jr $t9 ; branch delay slot, NOP
la $a0, ($LC0 & 0xFFFF) # "zero" ; branch delay slotloc_38: # CODE XREF: f+1C
lui $a0, ($LC3 >> 16) # "something unknown"
lw $t9, (puts & 0xFFFF)($gp)
or $at, $zero ; load delay slot, NOP
jr $t9
la $a0, ($LC3 & 0xFFFF) # "something unknown" ; branch delay slot
loc_4C: # CODE XREF: f+14
lui $a0, ($LC2 >> 16) # "two"
lw $t9, (puts & 0xFFFF)($gp)
or $at, $zero ; load delay slot, NOP
jr $t9
la $a0, ($LC2 & 0xFFFF) # "two" ; branch delay slot
loc_60: # CODE XREF: f+8
lui $a0, ($LC1 >> 16) # "one"
lw $t9, (puts & 0xFFFF)($gp)
or $at, $zero ; load delay slot, NOP
jr $t9
la $a0, ($LC1 & 0xFFFF) # "one" ; branch delay slot
The function always ends with callingputs(), so here we see a jump toputs()(JR: “Jump Register”)
instead of “jump and link”. We talked about this earlier:1.15.1 on page 154.
We also often seeNOPinstructions afterLWones. This is “load delay slot”: anotherdelay slotin MIPS.
An instruction next toLWmay execute at the moment whileLWloads value from memory.
However, the next instruction must not use the result ofLW.
Modern MIPS CPUs have a feature to wait if the next instruction uses result ofLW, so this is somewhat
outdated, but GCC still adds NOPs for older MIPS CPUs. In general, it can be ignored.
Conclusion
Aswitch()with few cases is indistinguishable from anif/elseconstruction, for example: listing.1.15.1.
1.15.2 A lot of cases
If aswitch()statement contains a lot of cases, it is not very convenient for the compiler to emit too large
code with a lotJE/JNEinstructions.
#include <stdio.h>
void f (int a)
{
switch (a)
{
case 0: printf ("zero\n"); break;
case 1: printf ("one\n"); break;
case 2: printf ("two\n"); break;
case 3: printf ("three\n"); break;
case 4: printf ("four\n"); break;
default: printf ("something unknown\n"); break;
};
};
int main()
{
f (2); // test
};