1.19. FLOATING-POINT UNIT
You can also see theTOPregister contents inStatus Word(line 44)—it is 6 now, so the stack top is now
pointing to internal register 6.
The values ofaandbare swapped afterFXCHis executed (line 54).
FUCOMIis executed (line 83). Let’s see the flags:CFis set (line 95).
FCMOVBEhas copied the value ofb(see line 104).
FSTPleaves one value at the top of stack (line 136). The value ofTOPis now 7, so the FPU stack top is
pointing to internal register 7.
ARM
Optimizing Xcode 4.6.3 (LLVM) (ARM mode)
Listing 1.216: Optimizing Xcode 4.6.3 (LLVM) (ARM mode)VMOV D16, R2, R3 ; b
VMOV D17, R0, R1 ; a
VCMPE.F64 D17, D16
VMRS APSR_nzcv, FPSCR
VMOVGT.F64 D16, D17 ; copy "a" to D16
VMOV R0, R1, D16
BX LR
A very simple case. The input values are placed into theD17andD16registers and then compared using
theVCMPEinstruction.
Just like in the x86 coprocessor, the ARM coprocessor has its own status and flags register (FPSCR^128 ),
since there is a necessity to store coprocessor-specific flags. And just like in x86, there are no conditional
jump instruction in ARM, that can check bits in the status register of the coprocessor. So there isVMRS,
which copies 4 bits (N, Z, C, V) from the coprocessor status word into bits of thegeneralstatus register
(APSR^129 ).
VMOVGTis the analog of theMOVGT, instruction for D-registers, it executes if one operand is greater than
the other while comparing (GT—Greater Than).
If it gets executed, the value ofais to be written intoD16(that is currently stored inD17). Otherwise the
value ofbstays in theD16register.
The penultimate instructionVMOVprepares the value in theD16register for returning it via theR0andR1
register pair.
Optimizing Xcode 4.6.3 (LLVM) (Thumb-2 mode)
Listing 1.217: Optimizing Xcode 4.6.3 (LLVM) (Thumb-2 mode)VMOV D16, R2, R3 ; b
VMOV D17, R0, R1 ; a
VCMPE.F64 D17, D16
VMRS APSR_nzcv, FPSCR
IT GT
VMOVGT.F64 D16, D17
VMOV R0, R1, D16
BX LR
Almost the same as in the previous example, however slightly different. As we already know, many
instructions in ARM mode can be supplemented by condition predicate. But there is no such thing in
Thumb mode. There is no space in the 16-bit instructions for 4 more bits in which conditions can be
encoded.
However,Thumb-2wasextendedtomakeitpossibletospecifypredicatestooldThumbinstructions. Here,
in theIDA-generated listing, we see theVMOVGTinstruction, as in previous example.
(^128) (ARM) Floating-Point Status and Control Register
(^129) (ARM) Application Program Status Register