48 Silicon chip Australia’s electronics magazine siliconchip.com.au
also has two trimpots (VR1 and VR2)
that are used to set the maximum data
rate and the minimum retransmission
delay; more on that later.
Receiver RX1 is powered continu-
ously from the 5V supply so that it
can receive a signal at any time. When
there is no signal to be received, its data
output pin delivers a high-frequency
random (noise) signal. That is due to
the automatic gain control (AGC) in
the receiver increasing gain until it is
receiving a signal, even if that signal
is just amplified noise.
When there is an actual 433MHz
signal to receive, the AGC reduces the
receiver’s gain to prevent internal clip-
ping, ie, so it is not overloaded due to
excessive gain. Since the AGC gain var-
ies at a relatively slow rate, when the
433MHz signal transmission stops, the
receiver output will be low for a few
hundred milliseconds before the AGC
action increases the gain sufficiently to
produce noise again.
The 433MHz transmitter and receiv-
er use an elementary modulation sys-
tem, known as amplitude shift keying
or ASK. When its input is high (one),
the transmitter produces a 433MHz
carrier. When its input is low (zero),
the 433MHz carrier transmission stops.
The data rate is usually fast enough
that the receiver gain does not vary
significantly during the burst, even
though during the zero bits, there is
no carrier.
There are various schemes which
exist to avoid having long periods of
all 0s or all 1s, regardless of the data
being transmitted, to help in cases like
this. One such scheme is Manchester
encoding, where each bit is encoded
as either a low (0) then a high (1), or a
high (1) then a low (0), at a fixed rate.
The UHF transmitter and receiver pair
can transfer data at up to 5kbits/second
using Manchester encoding.Distinguishing signal from
noise
The receiver’s AGC action poses
challenges for our software, since it
needs to be able to distinguish a se-
ries of zeros and ones that form part
of a genuine data transmission from
the zeros and ones that result from the
amplified noise in the receiver, when
there is no signal present.
IC1 monitors the signal from the
UHF receiver at its RB0 digital input
(pin 6). Each time the voltage level
changes, it decides whether it is just
due to noise or a valid data signal.
Valid data is determined by compar-
ing the received data rate to the maxi-
mum rate setting.
This is set using VR1, which also var-
ies the voltage at test point TP1. With
TP1 at 0V, the maximum data rate is
233bps, and with TP1 at 5V, the maxi-
mum data rate is 5kpbs. Intermediate
voltages give intermediate maximum
rate values.
If the incoming data rate is higher
than the rate setting of VR1, the data
is assumed to be noise and is rejected
as invalid (see Screen1).
If the data rate is less than the max-
imum data rate setting, the data is
considered valid and so it is stored in
memory. As soon as the data rate ex-
ceeds the maximum rate setting, it is
assumed that the transmission is com-
plete and so the data which has been
stored is then transmitted.This is done by reading the data out
of the RAM and feeding it to digital
output RA4 (pin 3) of IC1 at the same
rate that it was received. At the same
time, TX1, the UHF transmitter is pow-
ered up and transmits this stored data
(see Screen2).
IC2 is the memory that is used to
store the data. It is a 1024kbit random
access memory organised as 128k x
8-bit bytes. The memory is read and
written using via a Serial Peripheral
Interface (SPI).
When writing, data is sent to the SI
input of IC2 (pin 5) from the SDO (pin
8) output of IC1, one byte at a time.
When reading, data is sent from the
SO output of IC2 (pin 2) to the SDI in-
put (pin 7) of IC1; again, one byte at a
time. In both cases, the data is clocked
by a signal from the SCK (pin 10) of
IC1, which is fed TO the SCK input of
IC2 (pin 6).
The memory SPI interface is enabled
by a low level at the chip select (CS) in-
put (pin 1) of IC2, which is driven from
the RB3 digital output of IC1 (pin 9).
To write to the memory, the CS line
is brought low and then a write instruc-
tion is sent from IC1 to IC2, followed
by the memory address to write to. In
our application, this is always the first
location (address zero). This is a 24-
bit address sent as three 8-bit bytes.
The seven most significant address
bits are always zero since only 17 bits
are required to address the 128k bytes
in the RAM.
Following this, data can be written,
one byte at a time. By default, the ad-
dress is automatically incremented af-
ter each byte of data is written, so bytes
are written sequentially to the RAM.
We store the received data as 16-bit
values. The most significant bit (bit
15) indicates the received level, low
(0) or high (1). The remaining 15 bits
are used to store the duration that the
data stayed at that level. This period is
stored in increments of 4μs, resulting
in a 4μs minimum period and 131ms
maximum.
Reading data out of the memory is a
similar process to writing, except that
a different instruction is used and the
data is sent in the opposite direction,
from IC2 to IC1.Power saving features
Since we are powering the repeater
using solar panels and a small cell for
storage, its power consumption must
be minimised, especially when idleFig.2: this shows how the boost converter generates 5V to run the micro and
UHF transmitter and receiver from the 3.2-4.2V cell. The control circuit
pulses the base of internal transistor Q1 which pulls current from the cell
through inductor L1, charging up its magnetic field. When Q1 switches off,
that magnetic field collapses, D1 is forward-biased and CL charges up to 5V.
This is regulated by feedback to the control circuit via the voltage divider
formed by trimpot VR3 and a 10kΩ resistor.