Custom PC - UK (2020-05)

FEATURE / DEEP DIVE

be a variant of static RAM (SRAM). This

relies purely on a clever arrangement

of transistors to form a circuit that can

permanently store (so it’s static) a bit of

information, as long as power remains on.

This makes it ideally suited for large-scale

production alongside the many other

transistors that make up a CPU or GPU.

Moreover, SRAM is extremely quick, so it’s

the obvious choice for a memory technology

that sits closest to the processing units of

a CPU. However, because it requires six

transistors for every bit of information to be

stored, it’s very space-inefficient, making it

unrealistic as a means of producing larger

stores of main system memory.

At the other end of the scale, you have

memory such as the NAND flash that’s

used in SSDs. This memory also relies on

transistors, but a different type that can trap

a small electrical charge. These are great

for long-term storage, as the charge can be

trapped almost indefinitely even without

power. However, relatively speaking, it’s

very slow and you can also only write to it a

limited number of times, which is no good

for main system memory.

Instead, main system memory is made

up of dynamic RAM (DRAM). This uses just

a single transistor coupled with a single

capacitor to store one bit. The capacitor can

store an electrical charge, which denotes the

binary 1 or 0 depending on if it’s charged or

not, while the transistor is used to switch the

charge of the capacitor. This much simpler

arrangement is far more space-efficient than

SRAM, so it’s much cheaper to manufacture.

Its also much faster than NAND, and you can

write to it as many times as you like.

Crucially, though, DRAM is much slower

than SRAM, and it also requires the state

of each memory cell to be refreshed

continuously. This is because capacitors

quickly leak electrical charge, so the charge

has to be restored regularly. What’s more,

the mere act of reading the charge on the

capacitor drains it, meaning any read data

has to be written back again. This need to

constantly refresh the charge is in large part

why DRAM is so slow compared with SRAM.

CREATING MEMORIES

While the basic building block of DRAM

is the simple coupling of a capacitor

and a transistor, there is of course a lot

more involved with making a memory

module. The first step is stringing together

thousands of these cells into an efficient

grid arrangement (a memory array). Laid

out in this way, each cell can be located, or

addressed, according to the intersection of

the row and column in which it sits.

Connecting each row of cells is a single

pathway that’s known as the word line.

Meanwhile, each column is similarly

connected to a bit line (there are technically

two bit lines). These are so called because the

word line is the one that selects the portion

of data (the word) to be read or written, while

the bit lines are the ones that read or write the

1s and 0s (the bits) that make up that word.

Each entire row of the grid is called a page,

with multiple words making up each page.

Notably, data can only be read or written in

a minimum chunk size of a word. So, when

a read or write request arrives, we just need

to specify on which row the data sits and in

which column the word starts. Except, it’s a

bit more complicated than that, due to the

requirement to constantly be refreshing the

charge in the whole array, and because of

the way that simply reading a cell causes the

charge to be drained from the cell.

Regardless of whether you’re reading or

writing data, though, when interacting with a

DRAM array, the first step is the same. When

the memory request arrives, the row that’s

storing the data you need is activated by

sending a voltage to the row. This activates

the transistors in that row, connecting each

corresponding storage capacitor to its bit

line, which in turn causes the stored value of

the capacitor to be passed onto the bit line.

Because the charge from the capacitors

is so small, it requires amplifying to be read

correctly. As a result, all the data from the bit

lines for the entire row is sent through what

are appropriately called sense amplifiers,

which amplify the signal to a level at which

the rest of the system operates.

Once the whole row has been loaded

into the sense amplifiers, it’s then

considered active and sections (columns)

of it can be accessed for reading or writing.

Crucially, only one row per array can

be active at a time, making data access

BIT LINE

CAPACITOR

TRANSISTOR WORD LINE

Each bit of memory is made up of a single transistor and

capacitor connected to a bit line and word line

WHEN A READ OR WRITE REQUEST ARRIVES,

WE JUST NEED TO SPECIFY ON WHICH

ROW THE DATA SITS AND IN WHICH

COLUMN THE WORD STARTS

FEATURE / DEEP DIVE

be a variant of static RAM (SRAM). This

relies purely on a clever arrangement

of transistors to form a circuit that can

permanently store (so it’s static) a bit of

information, as long as power remains on.

This makes it ideally suited for large-scale

production alongside the many other

transistors that make up a CPU or GPU.

Moreover, SRAM is extremely quick, so it’s

the obvious choice for a memory technology

that sits closest to the processing units of

a CPU. However, because it requires six

transistors for every bit of information to be

stored, it’s very space-inefficient, making it

unrealistic as a means of producing larger

stores of main system memory.

At the other end of the scale, you have

memory such as the NAND flash that’s

used in SSDs. This memory also relies on

transistors, but a different type that can trap

a small electrical charge. These are great

for long-term storage, as the charge can be

trapped almost indefinitely even without

power. However, relatively speaking, it’s

very slow and you can also only write to it a

limited number of times, which is no good

for main system memory.

Instead, main system memory is made

up of dynamic RAM (DRAM). This uses just

a single transistor coupled with a single

capacitor to store one bit. The capacitor can

store an electrical charge, which denotes the

binary 1 or 0 depending on if it’s charged or

not, while the transistor is used to switch the

charge of the capacitor. This much simpler

arrangement is far more space-efficient than

SRAM, so it’s much cheaper to manufacture.

Its also much faster than NAND, and you can

write to it as many times as you like.

Crucially, though, DRAM is much slower

than SRAM, and it also requires the state

of each memory cell to be refreshed

continuously. This is because capacitors

quickly leak electrical charge, so the charge

has to be restored regularly. What’s more,

themereactofreadingthechargeonthe

capacitordrainsit, meaninganyreaddata

has to be written back again. This need to

constantly refresh the charge is in large part

why DRAM is so slow compared with SRAM.

CREATING MEMORIES

While the basic building block of DRAM

is the simple coupling of a capacitor

and a transistor, there is of course a lot

more involved with making a memory

module. The first step is stringing together

thousands of these cells into an efficient

grid arrangement (a memory array). Laid

out in this way, each cell can be located, or

addressed, according to the intersection of

the row and column in which it sits.

Connecting each row of cells is a single

pathway that’s known as the word line.

Meanwhile, each column is similarly

connected to a bit line (there are technically

two bit lines). These are so called because the

word line is the one that selects the portion

of data (the word) to be read or written, while

the bit lines are the ones that read or write the

1s and 0s (the bits) that make up that word.

Each entire row of the grid is called a page,

with multiple words making up each page.

Notably, data can only be read or written in

a minimum chunk size of a word. So, when

a read or write request arrives, we just need

to specify on which row the data sits and in

which column the word starts. Except, it’s a

bit more complicated than that, due to the

requirement to constantly be refreshing the

charge in the whole array, and because of

the way that simply reading a cell causes the

charge to be drained from the cell.

Regardless of whether you’re reading or

writing data, though, when interacting with a

DRAM array, the first step is the same. When

the memory request arrives, the row that’s

storing the data you need is activated by

sending a voltage to the row. This activates

the transistors in that row, connecting each

corresponding storage capacitor to its bit

line, which in turn causes the stored value of

thecapacitortobepassedontothebitline.

Becausethechargefromthecapacitors

is so small, it requires amplifying to be read

correctly. As a result, all the data from the bit

lines for the entire row is sent through what

are appropriately called sense amplifiers,

which amplify the signal to a level at which

the rest of the system operates.

Once the whole row has been loaded

into the sense amplifiers, it’s then

considered active and sections (columns)

of it can be accessed for reading or writing.

Crucially, only one row per array can

be active at a time, making data access

BIT LINE

CAPACITOR

TRANSISTOR WORD LINE

Each bit of memory is made up of a single transistor and

capacitor connected to a bit line and word line

WHEN A READ OR WRITE REQUEST ARRIVES,

WE JUST NEED TO SPECIFY ON WHICH

ROW THE DATA SITS AND IN WHICH

COLUMN THE WORD STARTS