FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

o

cg <= '0';
else
ca <= '1';
cb <= '1';
cc <= '1';
cd <= '1';
ce <= '1';
cf <= '1';
cg <= '1';
end if;
end if;
end loop;
end if;
end process;
end Behavioral;

Sync_VGA.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;

entity Sync_VGA is
Generic (
HVisibleArea: integer := 1024;
HFrontPorch_Dim: integer := 24;
HSync_Dim: integer := 136;
HBackPorch_Dim: integer := 160;
VVisibleArea: integer := 768;
VFrontPorch_Dim: integer := 3;
VSync_Dim: integer := 6;
VBackPorch_Dim: integer := 29);
Port ( clk : in STD_LOGIC;
HSync : out STD_LOGIC;
HAddr : out STD_LOGIC_VECTOR (11 downto 0);
VSync : out STD_LOGIC;
VAddr : out STD_LOGIC_VECTOR (11 downto 0);
en_q : out STD_LOGIC);
end Sync_VGA;

architecture Behavioral of Sync_VGA is

signal HAddr_buf: STD_LOGIC_VECTOR (11 downto 0) := (others => '0');

signal VAddr_buf: STD_LOGIC_VECTOR (11 downto 0) := (others => '0');