FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

x

HAddr <= HAddr_reg;

VAddr <= VAddr_reg;

en_q <= en_q_reg;

sync: Sync_VGA Port Map(

clk => clk,

HSync => HSync,

HAddr => HAddr_reg,

VSync => VSync,

VAddr => VAddr_reg,

en_q => en_q_reg);

R <= HAddr_reg(3 downto 0)

when

en_q_reg = '1' and

(HAddr_reg(5 downto 4) = "00" or

HAddr_reg(5 downto 4) = "11")

else

"0000";

G <= HAddr_reg(3 downto 0) when en_q_reg = '1' and HAddr_reg(4) = '1' else

"0000";

B <= HAddr_reg(3 downto 0) when en_q_reg = '1' and HAddr_reg(5) = '1' else

"0000";

end Behavioral;

testB_VGA_pattern.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity testB_VGA_pattern is
end testB_VGA_pattern;

architecture Behavioral of testB_VGA_pattern is
component VGA_pattern is
Port ( clk : in STD_LOGIC;
R : out STD_LOGIC_VECTOR (3 downto 0);
G : out STD_LOGIC_VECTOR (3 downto 0);
B : out STD_LOGIC_VECTOR (3 downto 0);
HSync : out STD_LOGIC;
VSync : out STD_LOGIC);
end component;