FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

(Cristian I.K_ntXI) #1
"0000000000000000",

"0000000000110000",

"0000000001110000",

"0000000011110000",

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"0000000110000000",

"0000000110000000",

"0000000110000000",

"0000000110000000",

"0001111111111000",

"0000000000000000",

"0000000000000000",

"0000011111110000",

"0000110000011000",

"0001100000001100",

"0000000000001100",

"0000000000011000",

"0000000000110000",

"0000000001100000",

"0000000011000000",

"0000000110000000",

"0000001100000000",

"0000011000000000",

"0000110000000000",

"0001100000000000",

"0001111111111000",

"0000000000000000",

"0000000000000000",

"0000011111110000",

"0000110000011000",

"0001100000001100",

"0000000000001100",

"0000000000011000",

"0000000000110000",

"0000000111100000",

"0000000000110000",

"0000000000011000",

"0000000000001100",

"0000000000001100",

"0001100000001100",

"0000110000011000",

"0000011111110000",

"0000000000000000",
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