FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

(Cristian I.K_ntXI) #1
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signal uart_tx_done: STD_LOGIC := '0';
signal vga_en_q: STD_LOGIC := '0';
signal ssd_display_counter: STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal led_switch_counter: STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal char_counter: integer range 0 to 11 := 0;
signal shift_reg_q: STD_LOGIC_VECTOR (15 downto 0) := (others => '0');

signal uart_tx_done_prev: std_logic := '0';
begin


led <= shift_reg_q and sw;

clk_gen: clk_wiz_0
Port Map(
clk_in1 => CLK100MHZ,
clk_out1 => clk65MHz
);

process(clk65MHz)
begin
if rising_edge(clk65MHz) then
if (HAddr(10 downto 4) = "0111101" and VAddr(9 downto 4) = "101110") then
adrChar <= "0001";
elsif (HAddr(10 downto 4) = "0000011" and VAddr(9 downto 4) = "000001") then
adrChar <= "0010";
else
adrChar <= "0000";
end if;
end if;
end process;

process(clk65MHz)
begin
if rising_edge(clk65MHz) then
if vga_en_q = '1' and ROM_extract_pixel_q = '1' then
vgaRed <= "1111";
vgaGreen <= "1111";
vgaBlue <= "1111";
else
vgaRed <= R_pattern;
vgaGreen <= G_pattern;
vgaBlue <= B_pattern;
end if;
end if;
end process;

vga_write_char: ROM_extract_pixel
Port Map(
clk => clk65MHz,
adrChar => adrChar,
adrLine => VAddr(3 downto 0),
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