FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

rr

end process;
end generate data_in_gen;
end generate reg_generated;
end Behavioral;

pkg_demo.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
use work.pkg_exp.all;

entity pkg_demo is
Port ( CLK100MHZ : in STD_LOGIC;
rst: in STD_LOGIC;
sw : in STD_LOGIC_VECTOR (15 downto 0);
LED: out STD_LOGIC_VECTOR (15 downto 0)
);
end pkg_demo;

architecture Behavioral of pkg_demo is
signal q_func: data_type := (others => '0');
signal q_proc: STD_LOGIC_VECTOR(WIDTH_LIMIT - 1 downto 0) := (others => '0');

signal shift_reg_ce : STD_LOGIC := '0';
signal shift_reg_load : STD_LOGIC := '1';
signal shift_reg_load_data : STD_LOGIC_VECTOR (7 downto 0) := x"0F";
signal shift_reg_q : STD_LOGIC_VECTOR (7 downto 0) := x"0F";
signal led_shift_counter: STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal prev_shift_reg_load: std_logic := '0';
begin

led(WIDTH_LIMIT - 1 downto 0) <= q_func;

led(2 * WIDTH_LIMIT - 1 downto WIDTH_LIMIT) <= q_proc;

led(15 downto 8) <= shift_reg_q;

led_ctrl: process(CLK100MHZ)

begin

if rising_edge(CLK100MHZ) then

if rst = '1' then

shift_reg_load <= '1';

led_shift_counter <= x"0000_0000";

shift_reg_load_data <= x"53";

else

if shift_reg_load = '1' then

shift_reg_load <= '0';

end if;

--if led_shift_counter < x"03DF_D23F" then

if led_shift_counter < x"0000_0004" then