36 PART | I ITS technology enablers
Ethernet (camera, lidar) or LVDS (camera, radar). The main objective is thus
to enhance the EPI general purpose and accelerator processor architecture, in
particular, the memory hierarchy, NoC, and the computing resources, to meet
the requirements of the high-integrity and the high-performance execution
partitions, while ensuring freedom of interference between these partitions as
mandated by the ISO 26262 functional safety standard. Other key objectives
are the consolidation of the “high-performance” software environment com-
pliant with adaptive AUTOSAR so that the integration of the sensor process-
ing, data fusion, and deep machine learning software frameworks becomes
possible.
3.3.2 RISC-V extensions for real-time computing
In order to support the requirements of perception tasks in automated vehicles,
it is necessary to develop processes that offer real-time predictions. For this
purpose, high-performance accelerators must be employed in order to guarantee
high response time. The refactoring for offering time-predictability functions
has to begin from the processing core, then to develop the appropriate memory
structure at a local level and the interface to connect to the back-end environ-
ment, the external memory, and any other external interfaces.
Several researchers currently investigate architecture extensions to the
RISC-V accelerator cores that enable time-predictability, or more specifi-
cally, the fully timing compositional property. This property states that worst-
case execution times (WCETs) at the global level are composed of WCETs at
the local level. It also implies that WCET of a core that has multiple resource
conflicts can be safely approximated by adding all the interference times
for accessing the resources to the core’s WCET without interferences. The
fully timing compositional property is based on the formation of a pipeline
that offers in-order instructions, has a local cache and an LRU replacement
policy. It is not compatible with superscalar execution or dynamic branch
prediction.
Based on the directives of the “RISC-V Instruction Set Manual Volume I:
User-Level ISA,” that recommends the “End-of-Group bits in Prefix” approach,
real-time computations can be based on a very-long instruction word (VLIW)
extension of the RISC-V ISA. As opposed to superscalar execution VLIW is a
core implementation technique that enables multiple instructions to be issued,
and is compatible with the fully timing compositional property. The motiva-
tion is to obtain a core that has the performance of an application core (e.g.,
ARM Cortex-A) while ensuring the timing predictability of a real-time core
(e.g., ARM Cortex-R). This approach will ensure the correct execution of any
standard RISC-V binary on the VLIW core, in single-issue mode. A simple
recompilation will enable the multiple-issue mode on this core. Moreover, other
extensions of the RISC-V architecture defined in the scope of the EPI consor-
tium such as vector unit will be compatible with this VLIW extension.