device which will react more-or-less
instantly to excessive voltage.
But like most zener-type devices,
the difference between the voltage at
which it will start to conduct current
and the voltage across it when a large
current is flowing is quite large. We’ve
selected the most suitable device pos-
sible, but it’s still not ideal.
The ‘working voltage’ for TVS1 is
defined as 5V but it’s designed to pass
only 1mA or so at 6.0V. The clamping
voltages are specified as 9.8V at 1A and
13.5V at 42A.
So clearly, we can’t rely on this de-
vice to protect the PC since it would
allow quite a high voltage to be fed
back in before taking effect. Hence our
dual-action strategy, with TVS1 there
to limit very brief, high-voltage excur-
sions (eg, a static discharge) and also
to ‘fill in the gaps’ for the short period
until Q1/REF1 are able to switch on
and shunt the fault current.
Protection for the signal lines
We’ve also included 3V transient volt-
age suppressor TVS2 and dual schottky
diodes D1 and D2 to protect against
damaging voltages being fed in via the
D+ and D– signal wires. This is unlike-
ly, since these lines normally go straight
to some sort of USB/serial adaptor or
micro on a development board, and so
there aren’t many exposed components
to accidentally short.
But it’s still possible that a high
voltage fed into your +5V rail (or
+3.3V rail, or some other supply point)
could damage the USB/serial adaptor
or microcontroller and allow current
to flow through into the D+ and/or D–
lines. So we decided that we should
provide at least some protection for
these lines, as well.
The half of dual diodes D1/D2 that
connects between ground and the
signal line prevents them from being
pulled too far below ground.
We’re using smaller diodes here
since a large diode would have too
much capacitance and would interfere
with USB signalling. But these diodes
are still rated at 300mA continuous
and 1.25A for 10ms, with a forward
voltage below 1V up to several hun-
dred milliamps. So they should pro-
vide decent protection.
TVS2 has a breakdown voltage of
around 3.6V at 1mA and a clamping
voltage of 6.5V at 25A. So the combina-
tion of D1/D2 and TVS2 should con-
duct significant current away from the
D+/D– lines well before their voltages
reach 5V. Most USB ports would not
be damaged by these voltages.
We can’t put a voltage suppressor
like TVS2 directly between the D+ and
D– lines and ground because it would
have far too much capacitance. But
the series diodes between D+/D– and
TVS2 have a much lower capacitance
that’s effectively in series with that of
TVS2, so they have virtually no effect
on signalling. We tested our prototype
with a ‘hi-speed’ USB card reader and
it functioned normally.Is it bulletproof?
In a word, no, but if it does fail, the USB
Port Protector is likely to fail in such a
way that it still protects your computer.
While our testing shows that it’s robust
and can handle significant overloads
without damage, if you apply just the
right (worst possible) combination ofFig.2: safe operating area (curves) for the ECH8102 PNP
transistor, used in this device as a protective shunt. The
vertical red line corresponds to a shunt voltage of 5.5V
and its intersection with the SOA curves shows how
long the transistor is guaranteed to survive at various
collector current levels.Fig.3: the fuse
blow time for
F1 (black) and
‘trip’ time for
PTC1 (blue)
at various
current levels.
The relevant
portion of Q1’s
SOA curve
from Fig.2 is
plotted in
red and you
can see
that F1 will
protect Q1
for fault
currents
above 2A.voltage and current, it may be pos-
sible to blow Q1 or TVS1 before fuse
F1 blows.
Still, our testing suggests that the
most likely outcome of a serious over-
load is for F1 to blow and at least it’s
cheap and (relatively) easy to replace.
The difficulty in designing a circuit
like this to be able to withstand any-
thing you can throw at it is that in order
to effectively protect against a high
current source being connected to the
VCC line, it needs to absorb quite a lot of
power in a brief period. And while the
PTC and/or fuse should ideally cut the
power to protect the other components,
they may not be fast enough.
Fig.2 shows the ‘safe operating area’
(SOA) curves for transistor Q1, taken
from the ECH8102 data sheet. We’ve
added a vertical red line to show the
typical voltage of about 5.5V across Q1
while it is conducting.
While this is a high-current transis-
tor, it is quite tiny, so if a high current
is applied, it will quickly overheat
and might fail. As shown in Fig.2,
it’s guaranteed to survive 24A at 5.5V
(132W!) for somewhere between
500 μ s and 1ms. For longer periods,
the maximum allowable current is
lower; around 3A (16.5W) for 10ms,
1.5A (8.25W) for 100ms and 300mA
(1.65W) continuously.
Beyond this it may survive – but
that isn’t guaranteed. Our testing has
shown that for a single pulse, these
ratings are very conservative. But it’s
good practice to design a circuit to stay
within these ratings.
The ‘trip’ times for PTC1 (blue) and
F1 (black) are shown in Fig.3. We’ve
also plotted the relevant portion of