Digital Logic Fundamentals Unit 6 – JK Flip-Flop
Exercise 1 – Static JK Flip-Flop Operation
EXERCISE OBJECTIVE
When you have completed this exercise, you will be able to demonstrate the truth table for a JK
flip-flop by measuring the output logic states for changes to the input logic states. You will
verify your results with an oscilloscope.
EXERCISE DISCUSSION
- The JK flip-flop used in this exercise is designated as an integrated circuit (IC) type 74LS76
flip-flop. - The PR input presets (sets) the Q output to logic 1.
- The CLR input clears (resets) the Q output to logic 0.
- The data inputs are J and K.
• A negative clock edge is required for the outputs (Q and Q) to respond to the logic states of
the J and K data inputs.- A logic 0 (L) at PR (PRESET) sets the JK flip-flop: Q is logic 1 (H) and Q-not is logic 0 (L).
• A logic 0 (L) at CLR (CLEAR) resets the JK flip-flop: Q is logic 0 (L) and Q is logic 1 (H).
- A logic 0 (L) at PR or CLR will override the J, K, and CLK inputs.
• A logic 0 (L) at the PR and CLR inputs causes Q and Q to be logic 1 (H); this output
condition is invalid.- When PR and CLR are both logic 1 (H), the following three logic conditions at data inputs J
and K cause the following Q and Q output logic states after a negative edge of the clock
signal.- A logic 0 (L) at J and K results in no output change after the clock signal.
2. A logic 1 (H) at J and a logic 0 (L) at K result in Q equal to logic 1 (H) and Q equal to
logic 0 (L) after the clock signal.3. A logic 0 (L) at J and a logic 1 (H) at K result in Q equal to logic 0 (L) and Q equal to
logic 1 (H) after the clock signal.- When the J and K inputs have complementary logic states, the JK flip-flop functions
basically as a clocked RS flip-flop. - PR and CLR are logic 1, and J and K have complementary logic states. After the next
negative edge of the clock signal, the Q output equals the J input logic state. - A logic 1 (H) at J and K results in the outputs changing (toggling) after every negative edge
of the clock signal. - With J and K held at logic 1, the JK flip-flop is configured as a T flip-flop (toggle flip-flop).
- When the clock is logic 1 (H) or logic 0 (L), there is no output change.
- Inputs PR, CLR, J, and K are logic 1. After the next negative edge of the clock signal, the Q