Digital Logic Fundamentals Unit 6 – JK Flip-Flop
- When the JK flip-flop is configured as a D-type flip-flop, the Q output equals the logic state
of the J input after every negative edge of the clock signal, and the Q output equals the
complement of J.- If the logic state of the J input changes and then returns, between negative clock transitions,
to its original logic state, the outputs do not change. - When the PR or CLR inputs are logic 0, the outputs are held in a set or reset condition.