Digital Logic Fundamentals Unit 9 – Data Bus Control
The output of an inverter is the complement of the input.
The output of an AND gate is high when both inputs are high.
When the enable input of a tri-state buffer is high, the output is the same as the input.
When the enable input is low, the output of a tri-state buffer is in a high impedance (high-Z)
state; the output is effectively disconnected from the output circuit and the input has no effect on
the output.
The operation of this circuit in controlling data transfer is discussed and demonstrated in the
following two exercises.