Digital Logic Fundamentals Unit 9 – Data Bus Control
Exercise 1 – Static Control of a Data Bus
EXERCISE OBJECTIVE
When you have completed this exercise, you will be able to demonstrate the function of the CS
signal and R/W signal in controlling data transfer by using the DATA BUS CONTROL circuit
block. You will verify your results by observing the logic states of control and data lines.
EXERCISE DISCUSSION
• The CS and R/W control signals are initiated by the CPU.
- The WRITE and READ signals are outputs to tri-state buffers that permit bidirectional data
transfer between an I/O device and CPU. - When the CS signal is low, the READ and WRITE gates are disabled.
• A high CS allows the logic state of R/W to affect the output of the READ and WRITE gates.
• The inverter between R/W and the WRITE gate ensures that the complement of the R/W
signal is input to the WRITE gate.- The READ and WRITE tri-state buffers do not interact because only one buffer is enabled.