Signals and Systems - Electrical Engineering

7.4 Practical Aspects of Sampling 443

and use the characterization of the quantizer given in Equation (7.24), we have then that the error
ε(nTs)is obtained from

ˆx(nTs)≤x(nTs)≤xˆ(nTs)+ 1 by subtractingxˆ(nTs) ⇒ 0 ≤ε(nTs)≤ 1 (7.25)

indicating that one way to decrease the quantization error is to make the quantization step 1 very
small. That clearly depends on the quality of the ADC. Increasing the number of bits of the ADC
makes 1 smaller (see Equation (7.23) where the denominator is 2 raised to the number of bits),
which will make the quantization error smaller.

In practice, the quantization error is considered random, and so it needs to be characterized proba-
bilistically. This characterization becomes meaningful only when the number of bits is large, and the
input signal is not a deterministic signal. Otherwise, the error is predictable and thus not random.
Comparing the energy of the input signal to the energy of the error, by means of the so-called signal-
to-noise ratio (SNR), it is possible to determine the number of bits that are needed in a quantizer to
get a reasonable quantization error.

nExample 7.5

Suppose we are trying to decide between an 8- and a 9-bit ADC for a certain application. The

signals in this application are known to have frequencies that do not exceed 5 KHz. The amplitude

of the signals is never more than 5 volts (i.e., the dynamic range of the signals is 10 volts, so that

the signal is bounded as− 5 ≤x(t)≤5). Determine an appropriate sampling period and compare

the percentage of error for the two ADCs of interest.

Solution

The first consideration in choosing the ADC is the sampling period, so we need to get an ADC

capable of sampling atfs= 1 /Ts> 2 fmaxsamples/sec. Choosingfs= 4 fmax=20 K samples/sec,

thenTs= 1 /20 msec/sample. Suppose then we look at an 8-bit ADC, which means that the quan-

tizer would have 2^8 =256 levels so that the quantization step is 1 = 10 /256 volts. If we use the

truncation quantizer given above the quantization error would be

0 ≤ε(nTs)≤ 10 / 256

If we find that objectionable we can then consider a 9-bit ADC, with a quantizer of 2^9 =512 levels

and the quantization step is 1 = 10 /512 or half that of the 8-bit ADC

0 ≤ε(nTs)≤ 10 / 512

So that by increasing 1 bit we cut the quantization error in half from the previous quantizer (in

practice, one of the 8 or 9 bits is used to determine the sign of the sampled value). Inputting a signal

of constant amplitude 5 into the 9-bit ADC gives a quantization error of[( 10 / 512 )/ 5 ]×100%=

( 100 / 256 )%≈0.4% in representing the input signal. For the 8-bit ADC it would correspond to a

0.8% error. n