SEMICONDUCTOR DEVICE PHYSICS AND DESIGN

8.2. JFET AND MESFET:CHARGE CONTROL 359

Ga te ( p+ or Sc ho ttk y ba rri er )

So ur ce Dr ai n

n-d op ed se mi co nduc to r

lo w co nduc ti vi ty se mi co nduc to r

h

h

Ac ti ve ch a nne l Su bs tr at e

• ––– ––

eVbi

Pa rt ia lly de pl et ed

ac ti ve re gion.

Vbi: bu ilt -i n po te nt ia l

eVG

Co mp le te ly de pl et ed

ac ti ve re gion.

VG < 0

(a )

(b )

(c )

Figure 8.3: (a) A schematic of a JFET or MESFET showing the source, drain, and gate. The
channel width of this device ish; (b) the band profile when the applied gate bias is zero as is the
source-drain bias; (c) the band profile with a negative gate bias so that the channel is depleted.