SEMICONDUCTOR DEVICE PHYSICS AND DESIGN

374 CHAPTER 8. FIELD EFFECT TRANSISTORS

whereCGis assumed to be constant (which is true for a MOSFET) and is the normalized capac-
itance of the gate. Therefore

IDS(sat)=σsEsZ=eμnCG(VG−VT)·

VDS(sat)

L

·Z

= eμnCG(VG−VT)·

(VG−VT)

L

·Z (8.3.29)

=

eμnCGZ

L

(VG−VT)^2

whereZis the device width.
This analysis assumed that the electric field along the length of the channel was uniform. A
more rigorous analysis which allows for resistance and hence field variation leads to a factor of
2 in the expression, giving

IDS(sat)=

eμnCGZ

2 L

(VG−VT)^2 (8.3.30)

Analytical derivation of the output conductance; high aspect ratio design

The output conductancegdis given by

gd=

∂ID

∂VD

∣∣

∣

∣V

G

(8.3.31)

For a particular value ofVG,IDis of the form

ID=

K(VG)

LI

(8.3.32)

Therefore
∂ID
∂VD

=−

K(VG)

L^2 I

·

∂LI

∂VD

=−

ID

LI

·

∂LI

∂VD

(8.3.33)

Realizing thatLI+LII=LgivesΔLI=−ΔLII, equation 8.3.33 can be written as

∂ID

∂VD

=

ID

LI

(

∂LII

∂VD

)

(8.3.34)

Also assumingLI>> LII, a reasonable assumption for long gate length devices(L≥ 0. 5 μm),
LImay be replaced byL,giving

gd

ID

L

(

∂LII

∂VD

)

(8.3.35)

To evaluate(∂LII/∂VD)let us consider equation 8.3.26 again. We can write

V(x, h)=Vpar−VG+

2 hEc

π

sinh

(πx

2 h

)

(8.3.36)