SEMICONDUCTOR DEVICE PHYSICS AND DESIGN

396 CHAPTER 8. FIELD EFFECT TRANSISTORS

Design Issues in HFET Technology

DESIGNISSUE NEED METHODOLOGY

1. Ohmic contact
   resistance

Minimize n+ cap layers, optimized alloying

schemes, ion implantation

2. Channel and
   access resistance

Minimize Ion implantation, high 2DEG

density-mobility product,

n+ cap layers

3. Substrate injection Minimize Quantum well structures, p-type
   buffers


4. Gate leakage Minimize Junction HFETs, insulated gate
   structures, gate recess, field plates


5. Parasitic
   capacitances

Minimize Low Κ dielectrics, lateral structures

preferred

6. Breakdown voltage Maximize Gate recess structures, high
   bandgap materials, field plates


7. Threshold voltage Control Etch-stop layers, controlled
   epitaxial growth

Table 8.1: Overview of technology issues that must be addressed in HFET design.

figure 8.24 along with a band diagram. The access resistance of the HFET is comprised of the
sheet resistance of then+cap layerRn+, the sheet resistance of the 2DEGR 2 DEG,andthe
interchannel resistance posed by the barrier to electron flow between the cap and the channel
Rint(see figure 8.24b). The total resistance can be modeled as a distributed network of all of
these components, as shown schematically in figure 8.24a.
Solutions to reducingRintare to reduce the barrier to electron flow from then+layer to the
2DEG channel, and to reduce the barrier to tunneling. The first is best achieved by increasing the
doping in then+layer so that it is very degenerate, causingEFto rise aboveEC. The second is
achieved by addingn+doping in the AlGaAs layer nearest to the surface, which in turn enhances
the surface electric field and thereby tunneling. A schematic diagram illustrating the benefits of
both these solutions is shown in figure 8.25.

8.7.2 Maximizing 2DEG Conductivity ......................

The 2DEG conductivity in MODFET structuresσis given by

σ=eμnns (8.7.1)