8.8. SMALL AND LARGE SIGNAL ISSUES 413
whereCGis the gate-to-channel capacitance and describes the relationship between the gate
voltage and the gate charge. The intrinsic transconductance is thus inversely proportional to the
carrier transit time. The gate capacitance can be characterized by the gate-source capacitance
CGSand the gate-drain capacitanceCDGshown in figure 8.39b.
We can also define the output conductancegD, which describes the effect of the drain bias on
the drain current as
gD=∂ID
∂VDS
∣
∣∣
∣
VGS(8.8.3)
In addition to the intrinsic circuit elements discussed above, important extrinsic parasitic ele-
ments are the gate resistanceRG, the drain resistanceRD, and the source resistanceRS,which
represents the series resistance of the ohmic contact and the channel region between the source
and the gate. Also, we have the drain-to-substrate and drain-to-channel capacitancesCDSand
CDCrespectively. These parameters lead to a simplified circuit model for the FET device shown
in figure 8.39. This figure shows the equivalent circuit based on the physical origin of the cir-
cuit elements discussed above. An important characterization parameter is the forward current
gain cutoff frequencyfτ, which is measured with the output short-circuited. The parameterfτ
defines the maximum frequency at which the current gain becomes unity. Figure 8.40 shows a
simplified AC equivalent circuit where the input resistances are condensed intoRiand the output
is represented byRDS=1/gD.
(^)
Figure 8.40: (a)Simplified A.C.π-model for the transistor used in this analysis, (b) definition of
short circuit current gain and (c) definition of maximum available power gain (d) definition of
large signal power gain for load line match.