Chapter 7
in the ground connection. For example, if the driver’s outputs are +5V and 0V
relative to the driver’s ground, and the driver’s ground is 7V more positive than
the receiver’s ground, the receiver’s inputs relative to the receiver’s ground will
be +12V and +7V (ignoring losses and noise in the differential lines). The com-
mon-mode voltage at the receiver’s inputs is:
((DriverOutputA - DriverOutputB) / 2 ) + DriverGroundVoltage - ReceiverGroundVoltage
or
((+5 - 0) / 2) + 7 = +9.5
which is within the +12V limit.
In the other direction, if the driver’s outputs are +5V and 0V and the driver’s
ground is 7V more negative than the receiver’s ground, the receiver’s inputs rel-
ative to the receiver’s ground will be +2V and -7V. The common-mode voltage
is:
((+5 - 0) / 2) - 7 = -4.5
which is within the -7V limit.3$
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7
Understanding the reason for the common-mode voltage limit requires looking
inside the chips. Figure 7-13 shows the internal circuits for a portion of a
two-way, half-duplex link. The components are as presented in National Semi-
conductor’s application note AN-409. A wire connects the outputs of the two
drivers. The receivers, termination, and the rest of the drivers’ circuits aren’t
shown, and a complete link would include a similar circuit for the other wire in
the differential pair.
A second wire connects the grounds of the two nodes. Each driver has a para-
sitic diode connection (D3 and D4) between the chip’s grounded substrate
(base material) and the collector of the output transistor. The parasitic diode is
a result of the physics of the semiconductor material that makes up the chip.
The chip’s ground pin also connects to the substrate.
Schottky diodes D1 and D2 prevent damaging substrate currents from flowing
when one of the drivers is on and the other is off. For example, if driver Y’s
ground potential is 5V less than driver Z’s, if D1 and D2 are replaced by direct
connections, current could flow in a loop through D4, Q1, and back to D4.
Series resistors in the ground wire would limit the current, but driver Y’s output
voltage would clamp at -0.7V due to the voltage drop across D4. Diode D2