Ports for Embedded Systems
Firmware accesses the PIC18F4520’s asynchronous serial port via a series of
registers. When a register bit enables and disables a feature, a value of 1 enables
the feature and zero disables the feature. 3
Registers hold received data, data waiting to transmit, and status and control
information for the port. Figure 11-1 shows how data travels between the port
pins and the CPU.! #5 5 5
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The EUSART receive data register (RCREG) holds up to two bytes of received
data in a first-in, first-out (FIFO) buffer. Firmware reads data from the buffer in
the same order as it was received.! #5
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The EUSART transmit data register (TXREG) holds one byte of data to trans-
mit.5
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The receive serial shift register (RSR) stores bits received on the RX pin. After
detecting a Stop bit, if RCREG has room, the RSR loads the received byte into
RCREG. If RCREG is full, the RSR waits and loads the byte when space
becomes available. Firmware can’t access the RSR directly.
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The transmit serial shift register (TSR) loads data from TXREG and writes the
bits to the TX pin. The TSR loads data when TXREG contains a byte to send
and the TSR is empty. Firmware can’t access the TSR directly.
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The transmit status and control register (TXSTA) contains bits used in config-
uring and enabling the port. The register also holds the optional ninth bit for
transmitting. To enable receiving 8-bit asynchronous data, set TXSTA to 20h
or 24h.