Chapter 11
For register bits that enable and disable specific interrupts or groups of inter-
rupts, a value of 1 enables the interrupt and a value of 0 disables the interrupt.
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The peripheral interrupt request register 1 (PIR1) contains bits that indicate the
status of individual peripheral interrupt sources.
Bit 5 (RCIF) indicates whether RCREG contains at least one byte (1) or is
empty (0).
Bit 4 (TXIF) indicates whether TXREG is full (0) or empty (1). The bit is set
to 1 when the TXSTA register’s TXEN bit is set to 1 and thereafter whenever
the TSR loads a byte to transmit from TXREG. The bit is set to zero when
firmware writes a byte to TXREG.
Note that RCIF = 1 when its buffer contains data and TXIF = 1 when its buffer
is empty. These are the conditions when firmware is likely to need to take
action. If the interrupts aren’t enabled, firmware can read the bits to learn the
states of the buffers.5
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The Reset Control Register (RCON) has one bit that can affect serial inter-
rupts.
Bit 7 (IPEN) enables priority levels on interrupts.
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The Peripheral Interrupt Priority Register 1 (IPR1) has two bits that set the
interrupt priority level for serial-port communications. These levels take effect
if the RCON register’s IPEN bit = 1. A value of 1 sets high priority, and zero
sets low priority. A high-priority interrupt will interrupt a low-priority interrupt
being serviced.
Bit 5 (RCIP) sets the receive interrupt priority.
Bit 4 (TXIP) sets the transmit interrupt priority."
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The interrupt control register (INTCON) has two bits that affect serial-port
interrupts. The functions of the bits vary depending on the value of the IPEN
bit in the RCON register.