Chapter 11
Interrupt Control Register 3 (INTCON3)
Bit 0 (INT1IF) and bit 1 (INT2IF) are set to 1 when their corresponding exter-
nal interrupts occur. Firmware must clear the bits.
Bit 3 (INT1IE) and bit 4 (INT2IE) enable their corresponding external inter-
rupts.
Bit 6 (INT1IP) and bit 7 (INT2IP) set the interrupt priority for their corre-
sponding interrupts. INT0 is always high priority.5
As explained earlier in this chapter, the PIC18F4520 has a 2-byte receive buffer
(RCREG) and a shift register (RSR) that stores the bits of an incoming byte. To
prevent overrun errors, firmware should de-assert the flow-control output when
both of the following are true: RCREG contains a byte, and the Stop bit of the
next byte might arrive at the RX pin before firmware can read RCREG.
For example, assume that the bit rate is 9600 bps with 8 data bits and 1 Stop
bit, and RCREG contains 1 byte. Another byte can arrive at the RSR and be
stored in RCREG in about 1 millisecond. If the flow-control output remains
asserted at this point, the remote computer will assume it’s OK to send a
another byte and may do so. On receiving the Stop bit of the next byte, if both
previously received bytes remain in RCREG, the RSR is unable to copy the new
byte into RCREG, the microcontroller generates an overrun error, and the
recently arrived byte is lost. Note that a slower bit rate gives the receiving com-
puter more time to retrieve received bytes from RCREG.
Many applications never need to de-assert the flow-control output. If firmware
can read RCREG at intervals shorter than the time required to transmit three
words, the buffer will never overflow.#
The example that follows demonstrates how to use hardware flow control. On
receiving a byte, the firmware de-asserts its flow-control output to tell the
remote computer not to send more data while the firmware is preparing its
response to the received byte. If the received byte is a code for a lower-case text
character (a–z), the receiving computer sends back the character converted to
upper case. Otherwise, the receiving computer sends back the same value
received. In either case, firmware waits for its flow-control input to be asserted
before sending the response.