In this model, the block scdspeed_compdelay/Computational Delay models the
effects of the computational delay. The delay is equal to the sample time of the controller,
which is the worst case. A zero order hold block scdspeed_compdelay/Zero-Order
Hold models the effect of sampling on the response of the system. Finally, the speed
controller (implemented with the PID Controller block) is discretized using a Forward
Euler sampling method.
You can see the effect of the sampling by simulating the response of the system.
First, discretize the controller at Ts = 0.1:
Ts = 0.1;
sim(mdl);
T2 = simout.time;
Y2 = simout.signals.values;
Next, discretize the controller at a increased sample time Ts = 0.25 seconds:
Ts = 0.25;
sim(mdl);
T3 = simout.time;
Y3 = simout.signals.values;
The second model is a continuous model.
mdl_continuous = 'scdspeed_contcomp';
open_system(mdl_continuous);
Modeling Computational Delay and Sampling Effects