Handbook for Sound Engineers

980 Chapter 25

Although there is from a component-count stand-
point a tendency to want to include the clocking genera-
tion in with an existing FPGA, say one from a mix
stage, it can be beneficial to have it stand alone in a
smaller FPGA or CPLD package. Generally, each clock
feed to each device should be individually buffered and
be as close to its target as possible. Needless to say, this
takes a lot of FPGA/CPLD pins, and a single-purpose
device starts looking like a good idea. The major benefit
is that one can physically locate it where it can do the
most good; this is as close as one can get it to the A/D,
D/A and sample-rate converters. Ideally (but rarely is it
possible) these should all be clustered in a “convertor
ghetto” to keep the clock lines really short and tight
from the clock generator, which minimizes noise and
slewing on the various clocks, which can directly affect
convertor jitter noise performance.

25.23.3 Signal-Processing Control

Fig. 25-150 outlines a typical control architecture for
signal processing, or the processing end. It should be
considered along with Fig. 25-124, which shows the
control-surface end. The separation reflects that often
the processing and the control are, indeed, in separate
places interconnected by a network.

25.23.3.1 Controlling the DSPs

Each of the DSPs has an SPI (serial peripheral interface)
port, an industry-standard means of device intercommu-
nication. This consists on each device of a serial clock

line, which synchronously clocks data in or out, and a

serial data in line; these may be paralleled around all the

DSPs. A serial data outline needs to be selected in a

multiplexer for feeding data (such as metering informa-

tion) back into the host processor. There is also a chip

select line, which needs to be run individually back to

the host; when yanked, a particular DSP knows that the

data being clocked out on the serial data line is for it.

It is down this SPI interface bus that the DSPs

receive their boot code at turn-on (the program code

which it will run), a set of working coefficients (usually

those that were current when the console was last turned

off), and any changes to those coefficients as the

console is being operated and parameters changed.

25.23.3.2 Metering

The indication to the user of the various channels’ and

groups’ signal levels, dynamics gain reduction values,

etc. is performed by the control-surface host, driving the

appropriate indicators. How the data gets to that micro

from the DSPs that are doing all the work can vary

widely in implementation depending mostly on the

physical configuration of the console. If it is a single

box, with the signal processing under the hood of the

control surface, then metering data can best be taken

simply and directly from GPIO (general-purpose input

and output) pins on the actual DSPs. Alternatively, but it

is giving up a major advantage of the one box, the host

micro could recover all the metering data from the

DSPs and distribute it all accordingly. If, though, the

Figure 25-150. Signal-processing control architecture.

386

Microcontroller

Signal processing

host

Paarameter changes

RAM

SPI

Metering data

Boot code,

Coefficient changes

SPI

Metering data

Flash RAM

Ethernet

interface

DSP

DSP

"

"

"

"

(More DSPs)

"

"

"

"

FPGA

DSP

SPI

Controller