Handbook for Sound Engineers

Digital Audio Interfacing and Networking 1471

may be used for the entire path from driver to receiver.

If Category 5 or greater UTP is used, distances of 400

meters unequalized or 800 meters with equalization are

possible.

39.3.4 Line Drivers

Just like AES3 cabling, line drivers are specified as

having a balanced output with an impedance of

110 :r20% over the entire frequency range from

100 kHz to 128 times the maximum frame rate. The

driver must be capable of delivering an output level

between 2–7 V (measured peak to peak) into a 110:

resistive termination directly across its output terminals

with no cable present. The balance must be good

enough so that any common mode output components

are at least 30 dB lower in level than the balanced

output signal.

The rise and fall times of the output, as measured

between the 10–90% amplitude points, must be no

faster than 5 ns, and no slower than 30 ns into a 110:

resistive termination directly across its output terminals

with no cable present. A fast rise and fall time often

improves the eye pattern at the receiver, but a slower

rise and fall time often results in lower electromagnetic

interference (EMI) radiated. Equipment must meet the

EMI limits of the country in which it is used.

Equalization must not be applied at the driven end of

the line.

39.3.5 Jitter

All digital equipment has the potential for introducing

jitter, or small timing variations in the output signal.

Extreme amounts of jitter can actually cause data errors.

More moderate amounts of jitter may not change the

actual data transmitted, but can lead to other ill effects.

An ideal D/A would ignore the jitter on the incoming

signal and perfectly produce the analog output based

solely on the data carried. Unfortunately many real-

world A/D and D/A converters are far from ideal, and

allow jitter to change or modulate the output. Therefore

keeping jitter low can have significant audible benefits.

AES3 divides the jitter at the output of a line driver

into two parts intrinsic and pass through. The pass

through portion of the jitter is due to jitter in the timing

reference used. If such an external timing reference is

used AES3 requires that there never be more than 2 dB

of jitter gain at any frequency. The external timing

reference may be derived from an AES3 input signal, or

from a digital audio reference signal (DARS), which is

an AES3 signal used as a clock reference as specified in

AES11. If cascades of digital devices are built where

each device uses as its clock reference the AES3 signal

received from the previous device in the chain, it is

possible for the pass through jitter to eventually increase

the output jitter to an unacceptable level.

Many of today’s better A/D and D/A converters

provide jitter attenuation from the timing reference,

Fig. 39-9.

Intrinsic jitter is measured with the equipment’s own

internal clock and with the equipment locked to an

effectively jitter free external reference clock. Intrinsic

jitter is measured through a minimum-phase one-pole

high-pass filter whose –3 dB down point is 700 Hz, and

which accurately provides that characteristic down to at

least 70 Hz. The pass band of the filter has unity gain.

Measuring at the transition zero crossings and through

the filter the jitter must be less than 0.025 unit intervals

(UI), Fig. 39-5.

39.3.6 Line Receivers

Just like AES3 cabling and line drivers, line receivers

are specified as having a balanced output with an

impedance of 110:r20% over the entire frequency

range from 100 kHz to 128 times the maximum frame

rate. The receiver must be capable of accepting an input

level of 2–7 V (measured peak to peak). Early versions

of AES3 required the receiver be able to accept 10 V.

Only one receiver may be connected to an AES3 line.

Early versions of AES3 permitted multiple receivers,

but it became clear this was not good practice and the standard was modified.

Figure 39-8. AES3 General Circuit Configuration. Note: If safety regulation so require, the signal grounds shown may also

be tied to an electrical life safety ground.

Line driver

C 1 T 1 C 2 R

Interconnecting

cable R C Receiver

3 T 2

R

Equalization

Note Note