Digital Audio Interfacing and Networking 147739.5.6 Remote Control Pulse StructureThe remote control pulses are added to the DPP voltage
and have a peak to peak amplitude of 2r0.2 V. They
carry information in the form of pulse width modulation.
For AES3 frame rates (FR) of 48 kHz or multiples
thereof the remote control data rate is 750 bit/s, while
for FR of 44.1 kHz or multiples thereof the remote
control data rate is 689 bit/s.
A logical 1 is represented by a pulse width of
(7 × 64)(8 FR), and must follow the preceding pulse at
an interval of (1 × 64)(8 FR). A logical 0 is represented
by a pulse width of (1 × 64)(8 FR), and must follow the
preceding pulse at an interval of (7 × 64)(8 FR). Thus
in both cases the total time used by a bit is 64FR, a byte
is (8 × 64)FR, and the combination of the command
and data bytes is (16 × 64)FR, if the FR is 44.1 kHz or
48 kHz.
It is possible that in the future an extended command
byte may be added preceding the existing command and
data bytes. In any case the entire sequence of extended
command byte (if defined in the future), command byte,
and data byte is sent with no interruptions in the flow of
pulses.
The minimum interval between the end of one
command and data bytes block and the beginning of the
next is (8 × 64)FR or a 1 byte interval. This allows
detection of the end of the command and data bytes and
for the data to be latched into the microphone.
The command byte is transmitted first, immediately
followed by the data byte. Within each byte the MSB is
transmitted first and the LSB last.
The rise and fall times of the pulses (measured from
the 10% and 90% amplitude points) is to be 10μs
r 5 μs, over the entire specified load range of
dc = 50–250 mA, Cload= 0–170 nF including the cable
capacitance, Fig. 39-13.39.5.7 SynchronizationA mode 2 AES3-MIC transmitter contains a VCXO and
a DAC that set its operating frequency. The corre-
sponding PLL resides in the AES3-MIC receiver. The
receiver sends a regular stream of control voltage
commands to the microphone using Direct Command 3
of the simple instruction set. The commands are
repeated not less than once every s, and can have 8
to 13 bits of resolution. The ADC and DAC must have
an accuracy of r½ LSB, and be monotonic.
If on power up a mode 2 AES3-MIC transmitter does
not see synchronization commands sent to it by the
receiver, it will run in mode 1 at its default sampling
rate or at the rate specified by the extended instruction
set if supported. If while running a mode 2 AES3-MIC
transmitter stops receiving synchronization commands,
it should hold the last value of control voltage sent to it
until synchronization commands are restored.
Mode 2 transmitters identify themselves to mode 2
receivers by means of a command that is part of the user
data bits in the AES3 data stream. When a mode 2
capable receiver sees this signal it switches to mode 2
operation.
AES42 specifies the mode 2 AES3-MIC receiver
characteristics for 48 kHz or 44.1 kHz operation. Since
there is a linear relationship between comparisonState 0 0 0 0 0 0 0 0 No equalization, default.
x x x x x x x x All other states, manufacturer specific
equalization.
Extended Commands 8 through 32 Reserved.
Extended Command 33 Manufacturer Specific Instruction begin.
Extended Command 34 Manufacturer Specific Instruction end.
Manufacturer Specific Instructions Are Under Consideration.Table 39-2. Direct Commands (Continued)(^1) / 6
Figure 39-13. AES42 command and data byte bit structure at a 48 kHz frame rate (FR).
Extended command
optional byte (future use) MSB LSB
Bit 7 Bit 6 ... Bit 0 ... Bit 1 Bit 0
DPP + 2 V
DPP
64/fs 64/8fs 7×64/8fs
133 ms 0.167 ms
8 × 64/fs
10.64 ms
Start
Time
End
min. 8 × 64/fs
10.64 ms
Command byte Data byte Break
"1" "0" "3" "0" "1"
1.167 ms