Handbook for Sound Engineers

812 Chapter 24

The economics of delay design dictate that a rela-
tively low sampling rate be used as this reduces the
amount of storage that is required for a given length of
signal. The number of storage locations required is the
product of the sample rate and the length of the delay.

The required cutoff rate of the antialias filter is gov-
erned by the separation of the upper frequency fc and the
Nyquist frequency fs/2. As these two frequencies
become closer, the number of poles required in the filter
increases, adding cost to the filter.

Antialias filters may be implemented as either ana-
log or digital circuits. A digital antialiasing filter still
requires some form of an analog antialias filter but
relies on a high rate of oversampling to ease the design
requirements. The digital filter does not have the
demanding memory requirements of the delay line, so it
can operate at a much higher sample rate than the stor-
age section.

24.4.2 Capturing a Sample

A sample and hold circuit takes a very fast snapshot
sample of the instantaneous voltage of an analog signal
and then changes into a hold mode to preserve that volt-
age. A hold circuit forces the amplitude of the sample to
have constant value throughout a sample period. In Fig.
24-14D, the sample amplitude is shown being set at the
beginning of the sample period.

A basic sample and hold circuit is shown in Fig.
24-17. The signal amplitude is frozen for a brief period
of time on a capacitor until the next sample period is
initiated, at which time the new signal amplitude is
transferred to the capacitor. The switch is momentarily
closed, under the control of the sample pulse, and then
reopened. The amplifier A 1 must have low-output
impedance to make it capable of driving enough cur-
rent to charge the capacitor to the appropriate voltage
during the brief ontime of the sampling pulse. The out-
put amplifier A 2 must have high-input impedance so as
not to draw excessive charge from the capacitor as any
leakage of current will cause a change in the voltage.
The capacitor should also be lowleakage to help hold
the voltage stable. An analog delay may be constructed
entirely out of sample and hold circuits that transfer
charge from one to another.

24.4.3 Errors in Sampling Magnitude

Any sampling system, digital or analog, will take a
finite time to convert the input voltage into a form suit-
able for storage. This time is called the aperture time

and relates to the amplitude resolution of the conver-

sion. The sampling error 'V is equal to the amount that

the input voltage, V, changes during the aperture time tD:

(24-3)

For a sinusoidal input with peak amplitude A

(24-4)

where,

Z is Sf.

The rate of change of voltage is greatest at the zero

crossing when t=0

(24-5)

Expressing this error, e, a fraction of full scale,

(24-6)

where,

V is voltage,

A is peak amplitude,

f is frequency,

tDis aperture time.

As an example, a 20 kHz signal samples to a resolu-

tion of 16 bits (1 part in 65,536 or 0.0000152) requires

an aperture time of 0.0000152/20,000S or 0.24 ns. This

is a very short time interval for an analog-to-digital con-

verter to operate in. A sample and hold circuit is used to

preserve the voltage long enough for the conversion to

take place. The aperture time of the system becomes the

open switch time of the sample and hold rather than the

conversion time of the analog-to-digital converter

(ADC).

Figure 24-17. A commonly used sample-and-hold circuit.

A 1 A 2

Switch driver

'VtDdV

dt

= ------ -

'VtD

d

dt

= ---- -AsinZt

'Vt= DAZZcos t

'Vt= DAZ

e 'V

2 A

=-------

=SftD