942 Chapter 25
zero-cross to occur. It can be zooming around setting up
other MDACs in the meantime or attending to other
microlike things. The circuit is addressed, the new gain
data serially clocked into the MDACs’ first buffer and
then the micro nudges high the ARM line. (The ARM
line needs only an instantaneous +5 V pulse; positive
feedback around the first comparator keeps it set. Like-
wise, it can if desired be nudged down to
dis-ARM—nice, but useless.) Comparators wait for the
applied audio signal to fall into a low near-zero signal
window, at which point an instantaneous strobe pulse for
the /LDs is generated, which latches the new gain data
into the MDAC ladder and simultaneously cancels the
ARMing.
This arrangement would not be the avenue best trav-
eled for dynamics, being that it takes a comparatively
long time to load in data and wait for zero-crossings,
limiting apparent responsiveness—VCAs are a far
better course for dynamics—but for anything else it
works a treat. With reasonably matched 12 bit MDACs
this gain-control circuit is virtually transparent and even
works well in high-Q filters and EQs. It’s still not inex-
pensive though, and the dawning realization of exactly
how many of these circuits (or DAC/VCAs) would be
necessary to fulfill complete automation of a decent size
mixing console, and just how much they’d all cost, has
quite a stunning effect.
25.16.4 Discrete Logic and Programmable Gate
Arrays
In the next few (as in many earlier) pages, some inter-
face circuitry will be described in seeming excruciating
detail; the literal approaches taken will be valid for
small or localized circumstances where discrete logic
makes sense and the tremendous advantages (cost,
board real estate) of integration into large-scale
programmable digital parts cannot be realized; where
the system is large enough, the detail serves as a road
map for what needs to be emulated in the PLD
(programmable logic device) or FPGA (field-program-
mable gate array). The ubiquity of these parts now has
led to a hardware design approach that is at once bold
yet somewhat alien to those who still remember
tape-and-dot layouts; everything on a board, say
switches, resolvers, converters, etc., are taken directly to
pins on a gate array; the interface to the host microcon-
troller is brought to the gate array; then how it’s all
interconnected, strategized, timed, polled, strobed, etc.
becomes a pure (software) programming exercise for
the gate array. Errors and changes similarly become just
software changes, too, not board re-spins.
25.16.5 Recall and ResetRemembering the position of controls in a conventional
console was the great innovative burst of the late 1970s.
The niceties of techniques vary, of course, but Figs.
25-112 to 25-116 are reasonably representative. The
great advantage of this sort of method is that it can be
applied to an existing design with virtually no modifica-
tion; all that’s required is a rider pot on the back of vari-
able controls (although this can be a bit difficult with
dual-concentric pots) and an extra pair of contacts on
switches.25.16.6 Data AcquisitionThe digital data-capture system is fairly straightforward.
Switch closures are sensed in batches of 8 (or 16 if a
large microcomputer or a minicomputer is in use), while
each individual pot position is resolved to the accuracy
afforded by an 8 bit analog-to-digital (A/D)
converter—256 possible positions. Although very high
for resolution and practical resetability of most pots, it
is actually harder work reducing the capability than
leaving it be! This may be true for pots, but with
high-quality faders it may seem too coarse; 12 bit reso-
lution may be necessary.
Two different types of input multiplexers are needed,
one for switch closure sensing and an analog switcher
for the rider-pot voltages. In computer thinking, each set
of eight switches and each rider-pot is regarded as a
single memory address; an entire console worth of
control settings occupies a chunk of the computer
memory map. It’s easy for the processor to run through
these addresses and collect a set of data.
In Fig. 25-112 a channel’s worth of multiplexing is
shown—32 switch sensings and 16 pots. Inexpensive
CMOS switchers are used throughout; speed isn’t a real
problem. The switch-sense multiplexers directly hit an 8
bit data bus, which can either be the actual processor
data bus (if the processor clock speed isn’t too fast for
the CMOS propagation delays) or, ordinarily, a buffered
sub-bus with slower timing. Speed freaks wondering
why things are almost deliberately slowed down should
remember two things:- A data acquisition system such as this running at
even a leisurely processor clock rate is quick! This
is not a real-time variable system, it’s intended
mostly for snapshot storage of console status; the
acquired data is really trivial by most processor
system standards. - The A/D conversion time for the pots keeps the
processor hanging about in wait states far longer